Every AI query initiates a data relay race: data leaves DRAM, hits the CPU for preprocessing, moves to the GPU for heavy math, then loops back—repeating for each generated token. This structural bottleneck forces every request through the industry's most expensive, power-hungry chips. XCENA, a four-year-old startup with offices in Pangyo and Sunnyvale, is attacking the problem at the physical layer: placing compute directly on the memory module.

Their chip, the MX1, connects to the CPU via CXL (Compute Express Link), processing data on the memory module before it ever needs to traverse the PCIe bus. “CPUs and GPUs both got smarter over decades. Memory never did,” said CEO Jin Kim, a Samsung and SK Hynix veteran. The bet is that inference is increasingly a memory-scaling problem, not just a compute one. The company claims a 10x server reduction for certain workloads.

Technically, the MX1 uses thousands of small, RISC-V-based cores optimized for data orchestration—preprocessing, KV cache management, and caching—tasks that currently pin CPU resources. Unlike Marvell or Astera Labs, which use a handful of general-purpose cores, XCENA designs its own memory hierarchy, interconnect bus, and DRAM controller in-house. This vertical integration gives them tighter control over latency and power, but also increases design risk.

The MX1 is still a prototype; mass production via Samsung's foundry is slated for late 2026, with revenue expected in 2027. The company just closed a $135M Series B at a $570M valuation, led by Altinum and IMM Investment. Ideal customers are hyperscalers where even a 5% memory efficiency gain can mean hundreds of millions in annual savings. The key engineering trade-off: betting that memory-centric architecture will matter more than raw GPU FLOPS for inference workloads.

Source: TechCrunch